Field effect transistors (FETs) employing compound semiconductors, such as gallium arsenide (GaAs) and indium phosphide (InP) are useful as high frequency transistors because electron mobilities in those semiconductors are relatively high. A conventional self-aligned field effect transistor in which the gate electrode is symmetrically disposed between the source and drain of the type described in Japanese Published Patent Application No. 62-166571 is shown in cross-section in FIG. 7. The gate electrode 2 is disposed on the surface of a semiconductor substrate 1 at an active layer 3 of the substrate. The active layer 3 generally has a relatively high conductivity and, in preferred embodiments, substrate 1 has a high resistivity and may be semi-insulating. The active layer 3 interconnects source and drain regions 4a and 4b. In the conventional self-aligned process, the gate electrode 2 is used as an ion implantation mask. As a result, the sides of the gate electrode 2 are aligned with the interfaces between the active layer 3 and the source and drain regions 4a and 4b. Generally, the gate electrode 2 is a heat-resistance material, such as a refractory metal or an alloy containing a refractory metal.
The FET structure of FIG. 7 has a relatively low gate-to-source resistance and good current-drive capability because the gate electrode 2 is directly adjacent the source and drain regions. However, when the FET of FIG. 7 is reduced in size, it can suffer from so-called short channel effects. Those within the active layer 3 when the same voltages are applied to a device with reduced channel length as are applied to devices with longer channel lengths. The strong electric field results in saturation of the velocity of the electrons traveling between the source and drain regions, limiting the transconductance and frequency response of the device. The positioning of the gate electrode 2 adjacent to the drain region 4b also limits the drain breakdown voltage to an undesirably low value. The low drain breakdown voltage limits the utility of the FET in linear integrated circuits and as a linear circuit element.
Another self-aligned FET structure of the type shown in FIG. 8 is also disclosed in Japanese Published Patent Application No. 62-166571. The elements of the structure of FIG. 8 are identical to those of the structure of FIG. 7 except that gate electrode 2 is symmetrically spaced from each of the source and drain regions 4a and 4b. The structure of FIG. 8 is produced in a self-aligned process by including ion implantation masks adjacent to the gate electrode 2 so that the source and drain regions are spaced suppresses the short channel effects because of the wide spacing between gate and source and that between the gate and drain. The separation of the gate electrode from the source and drain regions 4a and 4b increases the drain breakdown voltage but undesirably increases the gate-to-source resistance and reduces the current-drive capability of the device.
In response to these problems, an FET structure including a gate electrode that is asymmetrically disposed with respect to the source and drain regions has been proposed. One such proposed structure is shown in FIG. 9. In that structure, a groove is formed in the active layer 3 and the gate electrode 2 is asymmetrically disposed within the groove. This asymmetrically disposed gate electrode FET has a disadvantage in that it is not a self-aligned structure. However, the relatively small distance between the gate electrode 2 and the source region 4a results in a reduced gate-to-source resistance with a relatively high current-drive capability. The relatively large spacing between the gate electrode 2 and the drain region 4b increases the drain breakdown voltage. As a result, the transconductance of the FET is improved relative to the symmetrical gate structures of FIG. 7. However, it is difficult to repeatedly produce uniform FET structures like that of FIG. 9 in the absence of a self-aligned gate processing technique.
A method of making an FET with an asymmetrically disposed gate electrode and a relatively short gate length is described in Japanese Published Patent Application No. 62-86870 and illustrated in FIGS. 10(a) to 10(f). As shown in FIG. 10(a), a semi-insulating substrate 21 has an active layer 22 formed at the surface of the substrate. When the substrate 21 is GaAs, the active layer 22 is typically formed by ion implantation of silicon. A gate material 23, such as a refractory metal silicide, and an insulating film 28, for example, of silicon dioxide, are successively deposited on active layer 22. The gate material 23 and the insulating film 28 are formed into a desired gate electrode structure having a length corresponding to the drain-to-source region spacing. The gate length is defined by conventional photolithography techniques to produce the structure of FIG. 10(b).
A mask 29, such as a photoresist, is deposited to cover a portion of the active layer 22 where the source region will be produced on one side of the gate material 23 and on part of the top surface of the insulating film 28. The mask 29 is formed into the desired pattern by conventional techniques, leaving part of insulating film 28 exposed as illustrated in FIG. 10(c). That exposed portion of insulating film 28 is removed, for example, by etching, after which mask 29 is removed. Dopant ions are then implanted into the substrate 21 for a second time at a higher energy and with a larger dosage than employed to produce the active layer 22. This ion implantation step, which is conventionally followed by annealing, produces the structure of FIG. 10(d).
The asymmetrical disposition of the gate electrode relative to the source and drain regions 24 and 25 is completed by the removal of the portion of the gate material 23 that is not protected by the insulating film 28. The excess gate material is removed by wet or dry etching to produce the structure of FIG. 10(e). The insulating film mask 28 is subsequently removed and source and drain electrodes 26 and 27 are deposited on source and drain regions 24 and 25, respectively. The completed device structure, shown schematically in FIG. 10(f), includes the asymmetrically disposed gate electrode 23. Because the gate electrode is adjacent to the interface of the source region 24 with the active layer 22, the gate-to-source resistance is relatively low. The spacing between the gate electrode 23 and the drain region 25 enhances the current-drive capability and gate-to-drain breakdown voltage of the FET. However, the precise spacing between the gate electrode 23 and the drain region 25 is determined by the etching of the side wall of the gate electrode 23, a process that is difficult to control. Accordingly, the structure of FIG. 10(f) is difficult to reproduce uniformly. In addition, the exposure of a portion of the active layer 22 adjacent to the gate electrode 23 and all of the drain region 25 to a plasma when the unmasked portion of the gate material is dry etched damages the FET and degrades its performance.
In the FET structures of FIGS. 7-9 and 10(f), the formation of the source and drain regions is carried out simultaneously by ion implantation. As a result, those regions are generally symmetrical with respect to their depths and dopant concentrations. Another FET structure for suppressing short channel effects employs asymmetrically doped source and drain regions. Such a structure is shown in cross-section in FIG. 11 taken from FIG. 4 of Kimura et al, "Asymmetrical Implantation Self-alignment Technique For GaAs MESFETs", Japanese Journal of Applied Physics, Volume 27, No. 7, July 1988, pages L1340 to L1343. The self-aligned structure of FIG. 11 includes a source region 4A that is more heavily doped and deeper than is the drain region 4b. That result is achieved by carrying out three ion implantation steps in the course of making the FET rather than the two implantation steps employed in making the structures described above.
The structure of FIG. 11 is produced by masking a gate electrode 2 disposed on an active layer 3 formed in a substrate 1. The gate electrode 2 and the substrate are masked with an ion implantation mask material, such as germanium. An aperture is opened in the ion implantation mask near the gate electrode using a photoresist mask. Thereafter, ions are implanted through the aperture and in any adjacent areas where the implantation mask has been removed by side wall etching of the mask during opening of the aperture. Subsequently, the drain region is doped in another ion implantation step.
The method of making the asymmetrically doped FET disclosed by Kimura et al requires etching of the ion implantation mask beneath a photoresist mask. Complete removal of the ion implantation mask by side wall etching beneath the photoresist mask is essential to obtaining self-alignment of the source region and the gate electrode. Insufficient side wall etching can result in a non-uniform and undesired doping profile in the substrate. Excessive etching can result in damage to the gate electrode. Therefore, it is difficult to control processing and achieve uniformly reproducible results.
Accordingly, it is desirable to provide a process for self-aligningly producing field effect transistor structures incorporating the advantageous elements of the prior art structures but which is free of steps that are difficult to control and which affect the characteristics of the completed devices. In addition, it is desirable to provide new field effect transistor device structures produced by the novel method.